Logic circuitry package

ABSTRACT

A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, a request to turn on a clock generator of the logic circuitry package. The at least one logic circuit is configured to receive, via the interface, a request selecting an internal clock signal to sample. The at least one logic circuit is configured to receive, via the interface, a reference clock signal. The at least one logic circuit is configured to transmit, via the interface, a digital value indicating a count of cycles of the selected internal clock signal during a predetermined number of cycles of the reference clock signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This PCT Application claims the benefit of PCT Application No.PCT/US2019/026133, filed Apr. 5, 2019, entitled “LOGIC CIRCUITRY”; PCTApplication No. PCT/US2019/026152, filed Apr. 5, 2019, entitled “FLUIDPROPERTY SENSOR”; PCT Application No. PCT/US2019/026161, filed Apr. 5,2019, entitled “LOGIC CIRCUITRY”; and PCT Application No.PCT/US2018/063631, filed Dec. 3, 2018, entitled “LOGIC CIRCUITRY”; allof which are incorporated herein by reference.

BACKGROUND

Subcomponents of apparatus may communicate with one another in a numberof ways. For example, Serial Peripheral Interface (SPI) protocol,Bluetooth Low Energy (BLE), Near Field Communications (NFC) or othertypes of digital or analog communications may be used.

Some two-dimensional (2D) and three-dimensional (3D) printing systemsinclude one or more replaceable print apparatus components, such asprint material containers (e.g., inkjet cartridges, toner cartridges,ink supplies, 3D printing agent supplies, build material supplies etc.),inkjet printhead assemblies, and the like. In some examples, logiccircuitry associated with the replaceable print apparatus component(s)communicate with logic circuitry of the print apparatus in which theyare installed, for example communicating information such as theiridentity, capabilities, status and the like. In further examples, printmaterial containers may include circuitry to execute one or moremonitoring functions such as print material level sensing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one example of a printing system.

FIG. 2 illustrates one example of a replaceable print apparatuscomponent.

FIG. 3 illustrates one example of a print apparatus.

FIGS. 4A-4E illustrate examples of logic circuitry packages andprocessing circuitry.

FIG. 5A illustrates one example arrangement of a fluid level sensor.

FIG. 5B illustrates a perspective view of one example of a printcartridge.

FIG. 6 illustrates another example of processing circuitry.

FIG. 7 illustrates one example of a memory of a logic circuitry package.

FIG. 8 illustrates one example of a ring oscillator of a logic circuitrypackage.

FIG. 9 illustrates another example of processing circuitry.

FIGS. 10A-10B are flow diagrams illustrating one example of a methodthat may be carried out by a logic circuitry package.

FIGS. 11A-11B are flow diagrams illustrating another example of a methodthat may be carried out by a logic circuitry package.

FIGS. 12A-12D are flow diagrams illustrating another example of a methodthat may be carried out by a logic circuitry package.

FIGS. 13A-13D are flow diagrams illustrating another example of a methodthat may be carried out by a logic circuitry package.

FIGS. 14A-14B are flow diagrams illustrating another example of a methodthat may be carried out by a logic circuitry package.

FIG. 15 illustrates another example of a logic circuitry package.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific examples in which the disclosure may bepracticed. It is to be understood that other examples may be utilizedand structural or logical changes may be made without departing from thescope of the present disclosure. The following detailed description,therefore, is not to be taken in a limiting sense, and the scope of thepresent disclosure is defined by the appended claims. It is to beunderstood that features of the various examples described herein may becombined, in part or whole, with each other, unless specifically notedotherwise.

Some examples of applications described herein are in the context ofprint apparatus. Not all the examples, however, are limited to suchapplications, and at least some of the principles set out herein may beused in other contexts. The contents of other applications and patentscited in this disclosure are incorporated by reference.

In certain examples, Inter-integrated Circuit (I²C, or I2C, whichnotation is adopted herein) protocol allows at least one ‘master’integrated circuit (IC) to communicate with at least one ‘slave’ IC, forexample via a bus. I2C, and other communications protocols, communicatedata according to a clock period. For example, a voltage signal may begenerated, where the value of the voltage is associated with data. Forexample, a voltage value above X volts may indicate a logic “1” whereasa voltage value below X volts may indicate a logic “0”, where X is apredetermined numerical value. By generating an appropriate voltage ineach of a series of clock periods, data can be communicated via a bus oranother communication link.

Certain example print material containers have slave logic that utilizeI2C communications, although in other examples, other forms of digitalor analog communications could also be used. In the example of I2Ccommunication, a master IC may generally be provided as part of theprint apparatus (which may be referred to as the ‘host’) and areplaceable print apparatus component would comprise a ‘slave’ IC,although this need not be the case in all examples. There may be aplurality of slave ICs connected to an I2C communication link or bus(for example, containers of different colors of print agent). The slaveIC(s) may include a processor to perform data operations beforeresponding to requests from logic circuitry of the print system.

Communications between print apparatus and replaceable print apparatuscomponents installed in the apparatus (and/or the respective logiccircuitry thereof) may facilitate various functions. Logic circuitrywithin a print apparatus may receive information from logic circuitryassociated with a replaceable print apparatus component via acommunications interface, and/or may send commands to the replaceableprint apparatus component logic circuitry, which may include commands towrite data to a memory associated therewith, or to read data therefrom.

One example of logic circuitry associated with a replaceable printapparatus component may include a clock generation circuit. The clockgeneration circuit may include a ring oscillator to generate a ringoscillator clock signal, a system clock divider to generate a systemclock signal by dividing the ring oscillator signal based on a systemclock divider parameter, and a successive approximation register (SAR)clock divider to generate a SAR clock signal by dividing the ringoscillator signal based on a SAR clock divider parameter. The logiccircuitry may also include an oscillator test controller and a counterto sample a selected clock signal by counting the cycles of the selectedclock signal during a predetermined number of cycles of a referenceclock (e.g., I2C clock) signal. The cycle count may be used to determinethe frequency of the selected clock signal and to configure the clockdividers. The clock generation circuit may also include a dither counterto enable a dithered ring oscillator clock signal to reduceelectromagnetic interference (EMI).

In one example, a system integrity test may be performed by obtainingcycle counts for a selected clock signal during a predetermined numberof cycles of a first reference clock signal having a first frequency andduring the predetermined number of cycles of a second reference clocksignal having a second frequency. The obtained cycle counts shouldcorrespond to the respective reference clock frequencies. In anotherexample, a system integrity test may be performed by obtaining cyclecounts for a selected clock signal during a predetermined number ofcycles of a reference clock signal for a first dither point and a seconddither point of the selected clock signal. The obtained cycle countsshould correspond to the respective dither points. These two systemintegrity tests may also be combined into a single system integritytest.

In at least some of the examples described below, a logic circuitrypackage is described. The logic circuitry package may be associated witha replaceable print apparatus component, for example being internally orexternally affixed thereto, for example at least partially within thehousing, and is adapted to communicate data with a print apparatuscontroller via a bus provided as part of the print apparatus.

A ‘logic circuitry package’ as the term is used herein refers to onelogic circuit, or more logic circuits that may be interconnected orcommunicatively linked to each other. Where more than one logic circuitis provided, these may be encapsulated as a single unit, or may beseparately encapsulated, or not encapsulated, or some combinationthereof. The package may be arranged or provided on a single substrateor a plurality of substrates. In some examples, the package may bedirectly affixed to a cartridge wall. In some examples, the package mayinclude an interface, for example including pads or pins. The packageinterface may be intended to connect to a communication interface of theprint apparatus component that in turn connects to a print apparatuslogic circuit, or the package interface may connect directly to theprint apparatus logic circuit. Example packages may be configured tocommunicate via a serial bus interface. Where more than one logiccircuit is provided, these logic circuits may be connected to each otheror to the interface, to communicate through the same interface.

In some examples, each logic circuitry package is provided with at leastone processor and memory. In one example, the logic circuitry packagemay be, or may function as, a microcontroller or secure microcontroller.In use, the logic circuitry package may be adhered to or integrated withthe replaceable print apparatus component. A logic circuitry package mayalternatively be referred to as a logic circuitry assembly, or simply aslogic circuitry or processing circuitry.

In some examples, the logic circuitry package may respond to varioustypes of requests (or commands) from a host (e.g., a print apparatus). Afirst type of request may include a request for data, for exampleidentification and/or authentication information. A second type ofrequest from a host may be a request to perform a physical action, suchas performing at least one measurement. A third type of request may be arequest for a data processing action. There may be additional types ofrequests. In this disclosure, a command is also a type of request.

In some examples, there may be more than one address associated with aparticular logic circuitry package, which is used to addresscommunications sent over a bus to identify the logic circuitry packagewhich is the target of a communication (and therefore, in some examples,with a replaceable print apparatus component). In some examples,different requests are handled by different logic circuits of thepackage. In some examples, the different logic circuits may beassociated with different addresses. For example, cryptographicallyauthenticated communications may be associated with securemicrocontroller functions and a first I2C address, while othercommunications may be associated with a sensor circuit and a secondand/or reconfigured I2C address. In certain examples, these othercommunications via the second and/or reconfigured address can bescrambled or otherwise secured, not using the key used for the securemicrocontroller functions.

In at least some examples, a plurality of such logic circuitry packages(each of which may be associated with a different replaceable printapparatus component) may be connected to an I2C bus. In some examples,at least one address of the logic circuitry package may be an I2Ccompatible address (herein after, an I2C address), for example inaccordance with an I2C protocol, to facilitate directing communicationsbetween master to slaves in accordance with the I2C protocol. Forexample, a standard I2C communications address may be 7 or 10 bits inlength. In other examples, other forms of digital and/or analogcommunication can be used.

FIG. 1 illustrates one example of a printing system 100. The printingsystem 100 includes a print apparatus 102 in communication with logiccircuitry associated with a replaceable print apparatus component 104via a communications link 106. In some examples, the communications link106 may include an I2C capable or compatible bus (herein after, an I2Cbus). Although for clarity, the replaceable print apparatus component104 is shown as external to the print apparatus 102, in some examples,the replaceable print apparatus component 104 may be housed within theprint apparatus.

The replaceable print apparatus component 104 may include, for example,a print material container or cartridge (which could be a build materialcontainer for 3D printing, a liquid or dry toner container for 2Dprinting, or an ink or liquid print agent container for 2D or 3Dprinting), which may in some examples include a print head or otherdispensing or transfer component. The replaceable print apparatuscomponent 104 may, for example, contain a consumable resource of theprint apparatus 102, or a component which is likely to have a lifespanwhich is less (in some examples, considerably less) than that of theprint apparatus 102. Moreover, while a single replaceable printapparatus component 104 is shown in this example, in other examples,there may be a plurality of replaceable print apparatus components, forexample including print agent containers of different colors, printheads (which may be integral to the containers), or the like. In otherexamples, the print apparatus components 104 could include servicecomponents, for example to be replaced by service personnel, examples ofwhich could include print heads, toner process cartridges, or logiccircuit package by itself to adhere to corresponding print apparatuscomponent and communicate to a compatible print apparatus logic circuit.

FIG. 2 illustrates one example of a replaceable print apparatuscomponent 200, which may provide the replaceable print apparatuscomponent 104 of FIG. 1. The replaceable print apparatus component 200includes a data interface 202 and a logic circuitry package 204. In useof the replaceable print apparatus component 200, the logic circuitrypackage 204 decodes data received via the data interface 202. The logiccircuitry may perform other functions as set out below. The datainterface 202 may include an I2C or other interface. In certainexamples, the data interface 202 may be part of the same package as thelogic circuitry package 204.

In some examples, the logic circuitry package 204 may be furtherconfigured to encode data for transmission via the data interface 202.In some examples, there may be more than one data interface 202provided. In some examples, the logic circuitry package 204 may bearranged to act as a ‘slave’ in I2C communications.

FIG. 3 illustrates one example of a print apparatus 300. The printapparatus 300 may provide the print apparatus 102 of FIG. 1. The printapparatus 300 may serve as a host for replaceable components. The printapparatus 300 includes an interface 302 for communicating with areplaceable print apparatus component and a controller 304. Thecontroller 304 includes logic circuitry. In some examples, the interface302 is an I2C interface.

In some examples, controller 304 may be configured to act as a host, ora master, in I2C communications. The controller 304 may generate andsend commands to at least one replaceable print apparatus component 200,and may receive and decode responses received therefrom. In otherexamples the controller 304 may communicate with the logic circuitrypackage 204 using any form of digital or analog communication.

The print apparatus 102, 300 and replaceable print apparatus component104, 200, and/or the logic circuitry thereof, may be manufactured and/orsold separately. In an example, a user may acquire a print apparatus102, 300 and retain the apparatus 102, 300 for a number of years,whereas a plurality of replaceable print apparatus components 104, 200may be purchased in those years, for example as print agent is used increating a printed output. Therefore, there may be at least a degree offorwards and/or backwards compatibility between print apparatus 102, 300and replaceable print apparatus components 104, 200. In many cases, thiscompatibility may be provided by the print apparatus 102, 300 as thereplaceable print apparatus components 104, 200 may be relativelyresource constrained in terms of their processing and/or memorycapacity.

FIG. 4A illustrates one example of a logic circuitry package 400 a,which may for example provide the logic circuitry package 204 describedin relation to FIG. 2. The logic circuitry package 400 a may beassociated with, or in some examples affixed to and/or be incorporatedat least partially within, a replaceable print apparatus component 200.

In some examples, the logic circuitry package 400 a is addressable via afirst address and includes a first logic circuit 402 a, wherein thefirst address is an I2C address for the first logic circuit 402 a. Insome examples, the first address may be configurable. In other examples,the first address is a fixed address (e.g., “hard-wired”) intended toremain the same address during the lifetime of the first logic circuit402 a. The first address may be associated with the logic circuitrypackage 400 a at and during the connection with the print apparatuslogic circuit, outside of the time periods that are associated with asecond address, as will be set out below. In example systems where aplurality of replaceable print apparatus components are to be connectedto a single print apparatus, there may be a corresponding plurality ofdifferent first addresses. In certain examples, the first addresses canbe considered standard I2C addresses for logic circuitry packages 400 aor replaceable print components.

In some examples, the logic circuitry package 400 a is also addressablevia a second address. For example, the second address may be associatedwith different logic functions or, at least partially, with differentdata than the first address. In some examples, the second address may beassociated with a different hardware logic circuit or a differentvirtual device than the first address. The hardware logic circuit caninclude analog sensor functions. In some examples, the logic circuitrypackage 400 a may include a memory to store the second address (in someexamples in a volatile manner). In some examples, the memory may includea programmable address memory register for this purpose. The secondaddress may have a default second address while the second address(memory) field may be reconfigurable to a different address. Forexample, the second address may be reconfigurable to a temporary addressby a second address command, whereby it is set (back) to the defaultsecond address after or at each time period command to enable the secondaddress. For example, the second address may be set to its defaultaddress in an out-of-reset state whereby, after each reset, it isreconfigurable to the temporary (i.e., reconfigured) address.

In some examples, the package 400 a is configured such that, in responseto a first command indicative of a first time period sent to the firstaddress (and in some examples a task), the package 400 a may respond invarious ways. In some examples, the package 400 a is configured suchthat it is accessible via at least one second address for the durationof the time period. Alternatively or additionally, in some examples, thepackage may perform a task, which may be the task specified in the firstcommand. In other examples, the package may perform a different task.The first command may, for example, be sent by a host such as a printapparatus in which the logic circuitry package 400 a (or an associatedreplaceable print apparatus component) is installed. As set out ingreater detail below, the task may include obtaining a sensor reading.

Further communication may be directed to memory addresses to be used torequest information associated with these memory addresses. The memoryaddresses may have a different configuration than the first and secondaddress of the logic circuitry package 400 a. For example, a hostapparatus may request that a particular memory register is read out ontothe bus by including the memory address in a read command. In otherwords, a host apparatus may have a knowledge and/or control of thearrangement of a memory. For example, there may be a plurality of memoryregisters and corresponding memory addresses associated with the secondaddress. A particular register may be associated with a value, which maybe static or reconfigurable. The host apparatus may request that theregister be read out onto the bus by identifying that register using thememory address. In some examples, the registers may include any or anycombination of address register(s), parameter register(s) (for exampleto store clock enable, clock divider, and/or dither parameters), sensoridentification register(s) (which may store an indication of a type ofsensor), sensor reading register(s) (which may store values read ordetermined using a sensor), sensor number register(s) (which may store anumber or count of sensors), version identity register(s), memoryregister(s) to store a count of clock cycles, memory register(s) tostore a value indicative of a read/write history of the logic circuitry,or other registers.

FIG. 4B illustrates another example of a logic circuitry package 400 b.In this example, the package 400 b includes a first logic circuit 402 b,in this example, including a first timer 404 a, and a second logiccircuit 406 a, in this example, including a second timer 404 b. While inthis example, each of the first and second logic circuits 402 b, 406 ainclude its own timer 404 a, 404 b, in other examples, they may share atimer or reference at least one external timer. In a further example,the first logic circuit 402 b and the second logic circuit 406 a arelinked by a dedicated signal path 408. In other examples, that are notthe topic of FIG. 4B, a single integrated logic circuit may simulate thefunctions of the second logic circuit.

Back to FIG. 4B, in one example, the logic circuitry package 400 b mayreceive a first command including two data fields. A first data field isa one byte data field setting a requested mode of operation. Forexample, there may be a plurality of predefined modes, such as a firstmode, in which the logic circuitry package 400 b is to ignore datatraffic sent to the first address (for example, while performing atask), and a second mode in which the logic circuitry package 400 b isto ignore data traffic sent to the first address and to transmit anenable signal to the second logic circuit 406 a, as is further set outbelow. The first command may include additional fields, such as anaddress field and/or a request for acknowledgement.

The logic circuitry package 400 b is configured to process the firstcommand. If the first command cannot be complied with (for example, acommand parameter is of an invalid length or value, or it is notpossible to enable the second logic circuit 406 a), the logic circuitrypackage 400 b may generate an error code and output this to acommunication link to be returned to host logic circuitry, for examplein the print apparatus.

If, however, the first command is validly received and can be compliedwith, the logic circuitry package 400 b measures the duration of thetime period included in the first command, for example utilizing thetimer 404 a. In some examples, the timer 404 a may include a digital“clock tree”. In other examples, the timer 404 a may include an RCcircuit, a ring oscillator (as will be described below with reference toFIG. 8), or some other form of oscillator or timer. In yet otherexamples, the timer may include a plurality of delay circuits each ofwhich is set to expire after a certain time period, whereby depending onthe timer period indicated in a first command, the delay circuit ischosen.

In this example, in response to receiving a valid first command, thefirst logic circuit 402 b enables the second logic circuit 406 a andeffectively disables the first address, for example by tasking the firstlogic circuit 402 b with a processing task. In some examples, enablingthe second logic circuit 406 a includes sending, by the first logiccircuit 402 b, an activation signal to the second logic circuit 406 a.In other words, in this example, the logic circuitry package 400 b isconfigured such that the second logic circuit 406 a is selectivelyenabled by the first logic circuit 402 b. The first logic circuit 402 bis configured to use the first timer 404 a to determine the duration ofthe enablement, that is, to set the time period of the enablement.

In this example, the second logic circuit 406 a is enabled by the firstlogic circuit 402 b sending a signal via a signal path 408, which may ormay not be a dedicated signal path 408, that is, dedicated to enable thesecond logic circuit 406 a. In one example, the first logic circuit 402b may have a dedicated contact pin or pad connected to the signal path408, which links the first logic circuit 402 b and the second logiccircuit 406 a. In a particular example, the dedicated contact pin or padmay be a General Purpose Input/Output (a GPIO) pin of the first logiccircuit 402 b. The contact pin/pad may serve as an enablement contact ofthe second logic circuit 406 a.

In this example, the second logic circuit 406 a is addressable via atleast one second address. In some examples, when the second logiccircuit 406 a is activated or enabled, it may have an initial, ordefault, second address, which may be an I2C address or have some otheraddress format. The second logic circuit 406 a may receive instructionsfrom a master or host logic circuitry to reconfigure the initial secondaddress to a temporary second address. In some examples, the temporarysecond address may be an address which is selected by the master or hostlogic circuitry. This may allow the second logic circuit 406 a to beprovided in one of a plurality of packages 400 on the same I2C buswhich, at least initially, share the same initial second address. Thisshared, default, address may later be set to a specific temporaryaddress by the print apparatus logic circuit, thereby allowing theplurality of packages to have different second addresses during theirtemporary use, facilitating communications to each individual package.At the same time, providing the same initial second address may havemanufacturing or testing advantages.

In some examples, the second logic circuit 406 a may include a memory.The memory may include a programmable address register to store theinitial and/or temporary second address (in some examples in a volatilemanner). In some examples, the second address may be set following,and/or by executing, an I2C write command. In some examples, the secondaddress may be settable when the enablement signal is present or high,but not when it is absent or low. The second address may be set to adefault address when an enablement signal is removed and/or onrestoration of enablement of the second logic circuit 406 a. Forexample, each time the enable signal over the signal path 408 is low,the second logic circuit 406 a, or the relevant part(s) thereof, may bereset. The default address may be set when the second logic circuit 406a, or the relevant part(s) thereof, is switched out-of-reset. In someexamples, the default address is a 7-bit or 10-bit identification value.In some examples, the default address and the temporary second addressmay be written in turn to a single, common, address register. Forexample, while the first address of the first logic circuit is differentfor each different associated print material (e.g., different color inkshave different first addresses), the second logic circuits can be thesame for the different print materials and have the same initial secondaddress.

In the example illustrated in FIG. 4B, the second logic circuit 406 aincludes a first array 410 of cells and at least one second cell 412 orsecond array of second cells of a different type than the cells of thefirst array 410. In some examples, the second logic circuit 406 a mayinclude additional sensor cells of a different type than the cells ofthe first array 410 and the at least one second cell 412. Each of theplurality of sensor types may be identifiable by a different sensor ID,while each cell in a cell array of the same type may also beidentifiable by sensor ID. The sensor ID may include both the sensortype ID to select the array or type and the sensor cell ID to select thecell in the selected type or array, whereby the latter may also becalled “sub-”ID. The sensor IDs (including the sub-IDs) may include acombination of addresses and values, for example register addresses andvalues. The addresses of the sensor cell array ID and the sensor cell IDmay be different. For example, an address selects a register that has afunction to select a particular sensor or cell, and in the sametransaction, the value selects the sensor or cell, respectively. Hence,the second logic circuit may include registers and multiplex circuitryto select sensor cells in response to sensor IDs. In examples wherethere is only one cell of a certain sensor type, one sensor ID may besufficient to select that cell. At the same time, for that single sensorcell, different sensor “sub-”IDs will not affect the sensor cellselection because there is only one sensor cell. In this disclosure,sensor ID parameters are described. A sensor ID parameter may include asensor ID. A sensor ID parameter may include a sensor type ID or asensor cell ID. The same sensor ID (e.g., to select a sensor type) anddifferent sensor sub-IDs (e.g., to select a sensor cell) may be used toselect different sensor cells. The sensor ID parameters can include onlythe sensor sub-ID, for example where the sensor type has been previouslyset so that only the sensor cell needs to be selected.

The first cells 416 a-416 f, 414 a-414 f and the at least one secondcell 412 can include resistors. The first cells 416 a-416 f, 414 a-414 fand the at least one second cell 412 can include sensors. In oneexample, the first cell array 410 includes a print material level sensorand the at least one second cell 412 includes another sensor and/oranother sensor array, such as an array of strain sensing cells. Furthersensor types may include temperature sensors, resistors, diodes, cracksensors (e.g., crack sense resistors), etc.

In this example, the first cell array 410 includes a sensor configuredto detect a print material level of a print supply, which may in someexamples be a solid but in examples described herein is a liquid, forexample, an ink or other liquid print agent. The first cell array 410may include a series of temperature sensors (e.g., cells 414 a-414 f)and a series of heating elements (e.g., cells 416 a-416 f), for examplesimilar in structure and function as compared to the level sensor arraysdescribed in WO2017/074342, WO2017/184147, and WO2018/022038. In thisexample, the resistance of a resistor cell 414 is linked to itstemperature. The heater cells 416 may be used to heat the sensor cells414 directly or indirectly using a medium. The subsequent behavior ofthe sensor cells 414 depends on the medium in which they are submerged,for example whether they are in liquid (or in some examples, encased ina solid medium) or in air. Those which are submerged in liquid/encasedmay generally lose heat quicker than those which are in air because theliquid or solid may conduct heat away from the resistor cells 414 betterthan air. Therefore, a liquid level may be determined based on which ofthe resistor cells 414 are exposed to the air, and this may bedetermined based on a reading of their resistance following (at leastthe start of) a heat pulse provided by the associated heater cell 416.

In some examples, each sensor cell 414 and heater cell 416 are stackedwith one being directly on top of the other. The heat generated by eachheater cell 416 may be substantially spatially contained within theheater element layout perimeter, so that heat delivery is substantiallyconfined to the sensor cell 414 stacked directly above the heater cell416. In some examples, each sensor cell 414 may be arranged between anassociated heater cell 416 and the fluid/air interface.

In this example, the second cell array 412 includes a plurality ofdifferent cells that may have a different function such as differentsensing function(s). For example, the first and second cell array 410,412 may include different resistor types. Different cells arrays 410,412 for different functions may be provided in the second logic circuit406 a. More than two different sensor types may be provided, for examplethree, four, five or more sensor types, may be provided, wherein eachsensor type may be represented by one or more sensor cells. Certaincells or cell arrays may function as stimulators (e.g., heaters) orreference cells, rather than as sensors.

FIG. 4C illustrates an example of how a first logic circuit 402 c and asecond logic circuit 406 b of a logic circuitry package 400 c, which mayhave any of the attributes of the circuits/packages described above, mayconnect to an I2C bus and to each other. As is shown in the Figure, eachof the circuits 402 c, 406 b has four pads (or pins) 418 a-418 dconnecting to the Power, Ground, Clock, and Data lines of an I2C bus. Inanother example, four common connection pads are used to connect bothlogic circuits 402 c, 406 b to four corresponding connection pads of theprint apparatus controller interface. It is noted that in some examples,instead of four connection pads, there may be fewer connection pads. Forexample, power may be harvested from the clock pad; an internal clockmay be provided; or the package could be grounded through another groundcircuit; so that, one or more of the pads may be omitted or maderedundant. Hence, in different examples, the package could use only twoor three interface pads and/or could include “dummy” pads.

Each of the circuits 402 c, 406 b has a contact pin 420, which areconnected by a common signal line 422. The contact pin 420 of the secondcircuit serves as an enablement contact thereof.

In this example, each of the first logic circuit 402 c and the secondlogic circuit 406 b include a memory 423 a, 423 b. The memory 423 a ofthe first logic circuit 402 c stores information including cryptographicvalues (for example, a cryptographic key and/or a seed value from whicha key may be derived) and identification data and/or status data of theassociated replaceable print apparatus component. In some examples, thememory 423 a may store data representing characteristics of the printmaterial, for example, any part, or any combination of its type, color,color map, recipe, batch number, age, etc. The first logic circuit 402 cmay be, or function as, a microcontroller or secure microcontroller.

In this example, memory 423 b of the second logic circuit 406 b includesa programmable address register to contain an initial address of thesecond logic circuit 406 b when the second logic circuit 406 b is firstenabled and to subsequently contain a new (temporary) second address (insome examples in a volatile manner) after that new second address hasbeen communicated by the print apparatus. The new, e.g., temporary,second address may be programmed into the second address register afterthe second logic circuit 406 b is enabled, and may be effectively erasedor replaced at the end of an enablement period. In some examples, thememory 423 b may further include programmable registers to store any, orany combination of a read/write history data, cell (e.g., resistor orsensor) count data, Analog to Digital converter data (ADC and/or DAC),and a clock count, in a volatile or non-volatile manner. The memory 423b may also receive and/or store calibration parameters, such as offsetand gain parameters. Use of such data is described in greater detailbelow. Certain characteristics, such as cell count or ADC or DACcharacteristics, could be derivable from the second logic circuitinstead of being stored as separate data in the memory.

In one example, the memory 423 b of the second logic circuit 406 bstores any or any combination of an address, for example the second I2Caddress; an identification in the form of a revision ID; and the indexnumber of the last cell (which may be the number of cells less one, asindices may start from 0), for example for each of different cell arraysor for multiple different cell arrays if they have the same number ofcells.

In use of the second logic circuit 406 b, in some operational states,the memory 423 b of the second logic circuit 406 may store any or anycombination of timer control data, which may enable a timer of thesecond circuit, and/or enable frequency dithering therein in the case ofsome timers such as ring oscillators; a dither control data value (toindicate a dither direction and/or value); and a timer sample testtrigger value (to trigger a test of the timer by sampling the timerrelative to clock cycles measureable by the second logic circuit 406 b).

While the memories 423 a, 423 b are shown as separate memories here,they could be combined as a shared memory resource, or divided in someother way. The memories 423 a, 423 b may include a single or multiplememory devices, and may include any or any combination of volatilememory (e.g., DRAM, SRAM, registers, etc.) and non-volatile memory(e.g., ROM, EEPROM, Flash, EPROM, memristor, etc.).

While one package 400 c is shown in FIG. 4C, there may be a plurality ofpackages with a similar or a different configuration attached to thebus.

FIG. 4D illustrates an example of processing circuitry 424 which is foruse with a print material container. For example, the processingcircuitry 424 may be affixed or integral thereto. As already mentioned,the processing circuitry 424 may include any of the features of, or bethe same as, any other logic circuitry package of this disclosure.

In this example, the processing circuitry 424 includes a memory 426 anda first logic circuit 402 d which enables a read operation from memory426. The processing circuitry 424 is accessible via an interface bus ofa print apparatus in which the print material container is installed andis associated with a first address and at least one second address. Thebus may be an I2C bus. The first address may be an I2C address of thefirst logic circuit 402 d. The first logic circuit 402 d may have any ofthe attributes of the other examples circuits/packages described in thisdisclosure.

The first logic circuit 402 d is adapted to participate inauthentication of the print materials container by a print apparatus inwhich the container is installed. For example, this may include acryptographic process such as any kind of cryptographicallyauthenticated communication or message exchange, for example based on akey stored in the memory 426, and which can be used in conjunction withinformation stored in the printer. In some examples, a printer may storea version of a key which is compatible with a number of different printmaterial containers to provide the basis of a ‘shared secret’. In someexamples, authentication of a print material container may be carriedout based on such a shared secret. In some examples, the first logiccircuit 402 d may participate in a message to derive a session key withthe print apparatus and messages may be signed using a messageauthentication code based on such a session key. Examples of logiccircuits configured to cryptographically authenticate messages inaccordance with this paragraph are described in US patent publicationNo. 9619663.

In some examples, the memory 426 may store data including:identification data and read/write history data. In some examples, thememory 426 further includes cell count data (e.g., sensor count data)and clock count data. Clock count data may indicate a clock speed of afirst and/or second timer 404 a, 404 b (i.e., a timer associated withthe first logic circuit or the second logic circuit). In some examples,at least a portion of the memory 426 is associated with functions of asecond logic circuit, such as a second logic circuit 406 a as describedin relation to FIG. 4B above. In some examples, at least a portion ofthe data stored in the memory 426 is to be communicated in response tocommands received via the second address, for example the earliermentioned initial or reconfigured/temporary second address. In someexamples, the memory 426 includes a programmable address register ormemory field to store a second address of the processing circuitry (insome examples in a volatile manner). The first logic circuit 402 d mayenable read operation from the memory 426 and/or may perform processingtasks.

The memory 426 may, for example, include data representingcharacteristics of the print material, for example any or anycombination of its type, color, batch number, age, etc. The memory 426may, for example, include data to be communicated in response tocommands received via the first address. The processing circuitry mayinclude a first logic circuit to enable read operations from the memoryand perform processing tasks.

In some examples, the processing circuitry 424 is configured such that,following receipt of the first command indicative of a task and a firsttime period sent to the first logic circuit 402 d via the first address,the processing circuitry 424 is accessible by at least one secondaddress for a duration of the first time period. Alternatively oradditionally, the processing circuitry 424 may be configured such thatin response to a first command indicative of a task and a first timeperiod sent to the first logic circuit 402 d addressed using the firstaddress, the processing circuitry 424 is to disregard (e.g., ‘ignore’ or‘not respond to’) I2C traffic sent to the first address forsubstantially the duration of the time period as measured by a timer ofthe processing circuitry 424 (for example a timer 404 a, 404 b asdescribed above). In some examples, the processing circuitry mayadditionally perform a task, which may be the task specified in thefirst command. The term ‘disregard’ or ‘ignore’ as used herein withrespect to data sent on the bus may include any or any combination ofnot receiving (in some examples, not reading the data into a memory),not acting upon (for example, not following a command or instruction)and/or not responding (i.e., not providing an acknowledgement, and/ornot responding with requested data).

The processing circuitry 424 may have any of the attributes of the logiccircuitry packages 400 described herein. In particular, the processingcircuitry 424 may further include a second logic circuit wherein thesecond logic circuit is accessible via the second address. In someexamples, the second logic circuit may include at least one sensor whichis readable by a print apparatus in which the print material containeris installed via the second address. In some examples, such a sensor mayinclude a print materials level sensor. In an alternative example, theprocessing circuitry 424 may include a single, integral logic circuit,and one or more sensors of one or more types.

FIG. 4E illustrates another example of a first logic circuit 402 e andsecond logic circuit 406 c of a logic circuitry package 400 d, which mayhave any of the attributes of the circuits/packages of the same namesdescribed herein, which may connect to an I2C bus via respectiveinterfaces 428 a, 428 b and to each other. In one example the respectiveinterfaces 428 a, 428 b are connected to the same contact pad array,with only one data pad for both logic circuits 402 e, 406 c, connectedto the same serial I2C bus. In other words, in some examples,communications addressed to the first and the second address arereceived via the same data pad.

In this example, the first logic circuit 402 e includes amicrocontroller 430, a memory 432, and a timer 434. The microcontroller430 may be a secure microcontroller or customized integrated circuitryadapted to function as a microcontroller, secure or non-secure.

In this example, the second logic circuit 406 c includes atransmit/receive module 436, which receives a clock signal and a datasignal from a bus to which the package 400 d is connected, dataregisters 438, a multiplexer 440, a digital controller 442, an analogbias and analog to digital converter 444, at least one sensor or cellarray 446 (which may in some examples include a level sensor with one ormultiple arrays of resistor elements), and a power-on reset (POR) device448. The POR device 448 may be used to allow operation of the secondlogic circuit 406 c without use of a contact pin 420.

The analog bias and analog to digital converter 444 receives readingsfrom the sensor array(s) 446 and from additional sensors 450, 452, 454.For example, a current may be provided to a sensing resistor and theresultant voltage may be converted to a digital value. That digitalvalue may be stored in a register and read out (i.e., transmitted asserial data bits, or as a ‘bitstream’) over the I2C bus. The analog todigital converter 444 may utilize parameters, for example, gain and/oroffset parameters, which may be stored in registers.

In this example, there are different additional single sensors,including for example at least one of an ambient temperature sensor 450,a crack detector 452, and/or a fluid temperature sensor 454. These maysense, respectively, an ambient temperature, a structural integrity of adie on which the logic circuitry is provided, and a fluid temperature.

FIG. 5A illustrates an example of a possible practical arrangement of asecond logic circuit embodied by a sensor assembly 500 in associationwith a circuitry package 502. The sensor assembly 500 may include a thinfilm stack and include at least one sensor array such as a fluid levelsensor array. The arrangement has a high length to width aspect ratio(e.g., as measured along a substrate surface), for example being around0.2 mm in width, for example less than 1 mm, 0.5 mm, or 0.3 mm, andaround 20 mm in length, for example more than 10 mm, leading to lengthto width aspect ratios equal to or above approximately 20:1, 40:1, 60:1,80:1, or 100:1. In an installed condition the length may be measuredalong the height. The logic circuit in this example may have a thicknessof less than 1 mm, less than 0.5 mm, or less than 0.3 mm, as measuredbetween the bottom of the (e.g., silicon) substrate and the oppositeouter surface. These dimensions mean that the individual cells orsensors are small. The sensor assembly 500 may be provided on arelatively rigid carrier 504, which in this example also carries Ground,Clock, Power and Data I2C bus contacts.

FIG. 5B illustrates a perspective view of a print cartridge 512including a logic circuitry package of any of the examples of thisdisclosure. The print cartridge 512 has a housing 514 that has a width Wless than its height H and that has a length L or depth that is greaterthan the height H. A print liquid output 516 (in this example, a printagent outlet provided on the underside of the cartridge 512), an airinput 518 and a recess 520 are provided in a front face of the cartridge512. The recess 520 extends across the top of the cartridge 512 and I2Cbus contacts (i.e., pads) 522 of a logic circuitry package 502 (forexample, a logic circuitry package 400 a-400 d as described above) areprovided at a side of the recess 520 against the inner wall of the sidewall of the housing 514 adjacent the top and front of the housing 514.In this example, the data contact is the lowest of the contacts 522. Inthis example, the logic circuitry package 502 is provided against theinner side of the side wall. In some examples, the logic circuitrypackage 502 includes a sensor assembly as shown in FIG. 5A.

In other examples, a replaceable print apparatus component includes alogic circuitry package of any of the examples described herein, whereinthe component further includes a volume of liquid. The component mayhave a height H that is greater than a width W and a length L that isgreater than the height, the width extending between two sides.Interface pads of the package may be provided at the inner side of oneof the sides facing a cut-out for a data interconnect to be inserted,the interface pads extending along a height direction near the top andfront of the component, and the data pad being the bottom-most of theinterface pads, the liquid and air interface of the component beingprovided at the front on the same vertical reference axis parallel tothe height H direction wherein the vertical axis is parallel to anddistanced from the axis that intersects the interface pads (i.e., thepads are partially inset from the edge by a distance D). The rest of thelogic circuitry package may also be provided against the inner side.

It will be appreciated that placing logic circuitry within a printmaterial cartridge may create challenges for the reliability of thecartridge due to the risks that electrical shorts or damage can occur tothe logic circuitry during shipping and user handling, or over the lifeof the product.

A damaged sensor may provide inaccurate measurements, and result ininappropriate decisions by a print apparatus when evaluating themeasurements. Therefore, a method may be used to verify thatcommunications with the logic circuitry based on a specificcommunication sequence provide expected results. This may validate theoperational health of the logic circuitry.

FIG. 6 illustrates another example of processing circuitry 600.Processing circuitry 600 includes an interface (e.g., I2C interface)602, a clock generator 604, a clock generator test controller 606, and acounter 608. Interface 602 is electrically coupled to clock generatortest controller 606. An output of clock generator test controller 606 iselectrically coupled to a control input of counter 608. An input ofcounter 608 is electrically coupled to an output of clock generator 604.An output of counter 608 provides a result (i.e., count) on a resultsignal path 610.

Clock generator 604 generates a first clock signal. Clock generator 604may include a ring oscillator or another suitable clock generationcircuit. Clock generator test controller 606 receives a reference clocksignal (e.g., an I2C clock signal) through the interface 602. Counter608 is controlled by the clock generator test controller 606 to countcycles of the first clock signal generated by clock generator 604 duringa predetermined number of cycles of the reference clock signal. Thefrequency of the first clock signal may then be determined by dividingthe cycle count by the predetermined number of cycles of the referenceclock signal times the period of the reference clock signal. Thefrequency of the first clock signal may be used to determine whetherprocessing circuitry 600 is operating as expected and/or as part of avalidation process. The frequency of the first clock signal may also beused to determine clock divider parameters for setting the frequenciesof a second clock signal and/or a third clock signal based on the firstclock signal as will be described below with reference to FIG. 9.

FIG. 7 illustrates one example of a memory 612 of a logic circuitrypackage, such as logic circuitry package 400 a-400 d, or processingcircuitry 424. Memory 612 may include volatile or non-volatile memory.In one example, memory 612 includes registers. A first register 613 maystore most significant bits of a cycle count, such as the cycle countoutput by counter 608 of processing circuitry 600 of FIG. 6. A secondregister 614 may store least significant bits of the cycle count. Athird register 615 may store a system clock divider parameter for asystem clock signal, which may be a second clock signal based on thefirst clock signal generated by clock generator 604. A fourth register616 may store a successive approximation register (SAR) clock dividerparameter for a SAR clock signal, which may be a third clock signalbased on the first clock signal. A fifth register 617 may store a ditherparameter. As described below with reference to FIG. 8, the ditherparameter may be used to set a feedback path of a ring oscillator toadjust the frequency of the generated clock signal.

The system clock divider parameter, the SAR clock divider parameter, andthe dither parameter may be written to memory 612 by a print apparatuslogic circuit via an interface (e.g., an I2C interface). The cycle countmost significant bits and the cycle count least significant bits may beread by a print apparatus logic circuit via the interface. In oneexample, each register 613-617 is an 8-bit register.

FIG. 8 illustrates one example of a ring oscillator 620 of a logiccircuitry package, such as logic circuitry package 400 a-400 d, or ofprocessing circuitry 424 or 600. Ring oscillator 620 generates a ringoscillator clock signal on ring oscillator output signal path 632. Ringoscillator 620 includes an I2C interface 622, a dither register/counter624, a multiplexer 626, 128 stages 628 ₀ to 628 ₁₂₇, and 8 feedbackpaths 630 ₀ to 630 ₇. The input of stage 628 ₀ is electrically coupledto the ring oscillator output signal path 632 and is inverted. Theoutput of each stage (i.e., buffer) 628 ₀ to 628 ₁₂₆ is electricallycoupled to the input of the next stage 628 ₁ to 628 ₁₂₇, respectively.The output of each stage 628 ₁₂₀ to 628 ₁₂₇ is coupled to an input ofmultiplexer 626 through a corresponding feedback path 630 ₀ to 630 ₇.I2C interface 622 is electrically coupled to dither register/counter624. An output of dither register/counter 624 is electrically coupled tothe control input of multiplexer 626, and an input of ditherregister/counter 624 is electrically coupled to the ring oscillatoroutput signal path 632. The output of multiplexer 626 provides the ringoscillator clock signal on ring oscillator output signal path 632.

Dither register/counter 624 may receive a dither enable signal and/or adither parameter via I2C interface 622. Dither register/counter 624controls multiplexer 626 to select feedback paths 630 ₀ to 630 ₇ togenerate the ring oscillator clock signal having slightly differentfrequencies. With dithering enabled, electromagnetic interference (EMI)is reduced. When dithering is enabled, an auto-reversing up/down counter(e.g., a 3-bit counter) of dither register/counter 624 may be clocked bythe ring oscillator output to control the feedback path based on thecounter value. For example, a triangle wave type of dithering may beused, where the feedback points over time (periods) of the 128 stagering oscillator would be (by stage number): 120, 121, 122, 123, 124,125, 126, 127, 126, 125, 124, 123, 122, 121, 120, 121, 122, etc. Thisresults in a (mathematical) frequency dither of +/−2.81% from theaverage (dithered) frequency. The actual dither may be around +/−3.2%,since the circuit may include some additional fixed delays. Whendithering is disabled, the feedback path may be selected based on thedither parameter stored in the dither register of ditherregister/counter 624.

Ring oscillator 620 may be sensitive to process, voltage, andtemperature (PVT) variations, but may be divided down to generateinternal clock signals having desired frequencies as will be describedbelow with reference to FIG. 9. In this way, a more PVT tolerant designor fabrication trimming process is not needed, thus reducing thecomplexity and the cost of ring oscillator 620. In one example, the ringoscillator clock signal may have a frequency of about 18 MHz, while thedivided down internal clock signals may have a frequency of about 1 MHz.In other examples, the ring oscillator clock signal and the divided downinternal clock signals may have other suitable frequencies.

FIG. 9 illustrates another example of processing circuitry 640.Processing circuitry 640 includes an I2C interface 642, an oscillatortest controller 644, a ring oscillator 646, a dither counter 648, amultiplexer 650, a system clock divider 652, a SAR clock divider 654, amultiplexer 656, a counter 658, and a result register(s) 660. I2Cinterface 642 may be communicatively coupled to a print apparatus logiccircuit through a communication path 662. 120 interface 642 iscommunicatively coupled to an input of dither counter 648 through asignal path 664, to oscillator test controller 644 through a signal path666, and to the output of result register(s) 660 through a signal path668. Oscillator test controller 644 is electrically coupled to a controlinput of counter 658 through a signal path 670.

Dither counter 648 receives an enable signal through an enable ditheringsignal path 672. An output of dither counter 648 is electrically coupledto a control input of ring oscillator 646 through a signal path 674, andin input of dither counter 648 is electrically coupled to an output ofring oscillator 646 through a signal path 676. An enable input of ringoscillator 646 receives an enable signal through an enable oscillatorsignal path 678. The clock output of ring oscillator 646 is electricallycoupled to a first data input (i.e., input 0) of multiplexer 650 througha signal path 680. A second data input (i.e., input 1) of multiplexer650 receives an I2C test clock through an I2C test clock signal path682. The control input of multiplexer 650 receives a test mode enablesignal through a test mode enable signal path 684.

The output of multiplexer 650 is electrically coupled to a clock inputof system clock divider 652, a second data input (i.e., input 1) ofmultiplexer 656, and a clock input of SAR clock divider 654 through asignal path 686. The control input of system clock divider 652 receivesa system clock divider value through a system clock divider value signalpath 688. The clock output of system clock divider 652 provides thesystem clock and is electrically coupled to a first data input (i.e.,input 0) of multiplexer 656 through a system clock signal path 690. Thecontrol input of SAR clock divider 654 receives a SAR clock dividervalue through a SAR clock divider value signal path 692. The clockoutput of SAR clock divider 654 provides the SAR clock and iselectrically coupled to a third data input (i.e., input 2) ofmultiplexer 656 through a SAR clock signal path 694. The control inputof multiplexer 656 receives a test clock select signal on a test clockselect signal path 696. The output of multiplexer 656 is electricallycoupled to the input of counter 658 through a signal path 698. Theoutput of counter 658 is electrically coupled to the input of resultregister(s) 660 through a signal path 699.

I2C interface 642 may receive write commands from a print apparatuslogic circuit that include a system clock divider parameter, a SAR clockdivider parameter, an enable oscillator parameter, an enable ditheringparameter, a test mode enable parameter, and a test clock selectparameter. The parameters may be stored in a memory (not shown), such asregisters, of the processing circuitry 640. The parameters are passed tothe respective signal paths 688, 692, 678, 672, 684, and 696 to controlthe respective components 652, 654, 646, 648, 650, and 656.

Ring oscillator 646 may be provided by ring oscillator 620 previouslydescribed and illustrated with reference to FIG. 8. Ring oscillator 646is enabled in response to an enable oscillator signal on signal path678. With ring oscillator 646 enabled, a ring oscillator clock signal isoutput on signal path 680. With ring oscillator 646 disabled, no signalis output on signal path 680. In some examples, the ring oscillatorclock signal may be referred to as a first clock signal. As previouslymentioned, the ring oscillator clock signal may have a frequency ofabout 18 MHz or another suitable frequency.

Dither counter 648 is enabled in response to an enable dithering signalon signal path 672. With dithering enabled, dither counter 648 is activeand varies the feedback path of ring oscillator 646 based on the currentcounter value output on signal path 674 to generate a dithered ringoscillator clock signal. With dithering enabled, the count of dithercounter 648 is updated with every cycle of the ring oscillator clocksignal on signal path 676. When dithering is disabled, the feedback pathof ring oscillator 646 may be selected based on a dither parameterwritten to processing circuitry 640 (e.g., via I2C interface 642) by aprint apparatus logic circuit.

Multiplexer 650 passes one of the ring oscillator clock single and the120 test clock signal to signal path 686 based on the test mode enablesignal on signal path 684. In response to a first value of the test modeenable signal on signal path 684 corresponding to input 0 of multiplexer650, multiplexer 650 passes the ring oscillator clock signal on signalpath 680 to signal path 686. In response to a second value of the testmode enable signal on signal path 684 corresponding to input 1 ofmultiplexer 650, multiplexer 650 passes the I2C test clock signal onsignal path 682 to signal path 686. The I2C test clock signal may bereceived through I2C interface 642 and may be used to test processingcircuitry 640 to determine whether processing circuitry 640 is operatingas expected or as part of a validation process of processing circuitry640.

System clock divider 652 provides a first clock divider to generate asystem clock (i.e., a second clock signal) on system clock signal path690 based on the ring oscillator clock signal on signal path 686 (i.e.,with multiplexer 650 passing the ring oscillator clock signal). Systemclock divider 652 divides the ring oscillator clock signal based on thesystem clock divider value on signal path 688. In one example, systemclock divider 652 is an 8-bit divider. The system clock is the mainclock used to operate the logic circuitry package.

SAR clock divider 654 provides a second clock divider to generate a SARclock (i.e., a third clock signal) on SAR clock signal path 694 based onthe ring oscillator clock signal on signal path 686 (i.e., withmultiplexer 650 passing the ring oscillator clock signal). SAR clockdivider 654 divides the ring oscillator clock signal based on the SARclock divider value on signal path 692. In one example, SAR clockdivider 654 is a 6-bit divider. The SAR clock is used to operate asuccessive approximation analog to digital converter of the logiccircuitry package.

Multiplexer 656 provides a selection circuit to pass one of the ringoscillator clock signal (i.e., the first clock signal with multiplexer650 passing the ring oscillator clock signal), the system clock signal(i.e., the second clock signal), and the SAR clock signal (i.e., thethird clock signal) to the counter 658 based on the test clock selectsignal on signal path 696. In response to a first value of the testclock select signal on signal path 696 corresponding to input 0 ofmultiplexer 656, multiplexer 656 passes the system clock signal onsignal path 690 to signal path 698. In response to a second value of thetest clock select signal on signal path 696 corresponding to input 1 ofmultiplexer 656, multiplexer 656 passes the ring oscillator clock signalon signal path 686 to signal path 698. In response to a third value ofthe test clock select signal on signal path 696 corresponding to input 2of multiplexer 656, multiplexer 656 passes the SAR clock signal onsignal path 694 to signal path 698.

Counter 658 is controlled by oscillator test controller 644 throughsignal path 670 to count cycles of the selected clock signal on signalpath 698 during a predetermined number of cycles of a reference clocksignal. The reference clock signal may be an I2C clock signal receivedthrough the I2C interface 642. In one example, the I2C clock signal maybe provided as part of the command to sample the selected clock signal.In one example, the predetermined number of cycles is 8 cycles. In otherexamples, the predetermined number of cycles may include anothersuitable number of cycles.

The cycle count for the selected clock signal is written to resultregister(s) 660. In one example, result register(s) 660 includes a first8-bit register to store the most significant bits of the cycle count anda second 8-bit register to store the least significant bits of the cyclecount. In this case, a first read command from a print apparatus logiccircuit may be received through the I2C interface 642 to read the first8-bit register, and a second read command from the print apparatus logiccircuit may be received through the I2C interface 642 to read the second8-bit register.

The cycle count of the selected clock signal may be used by the printapparatus logic circuit to determine the frequency of the selected clocksignal by dividing the cycle count by the predetermined number of cyclesof the I2C clock signal times the I2C clock period. The frequency of theselected clock signal may be used by the print apparatus logic circuitto adjust and/or verify the system clock divider parameter and the SARclock divider parameter such that the system clock and the SAR clockhave the desired frequencies. In one example, the system clock dividerparameter and the SAR clock divider parameter are selected such that thesystem clock and the SAR clock both have a frequency of about 1 MHz. Inother examples, the system clock divider parameter and the SAR clockdivider parameter are selected such that the system clock and the SARclock have other suitable frequencies.

In some examples, processing circuitry 640 may be used to first measurethe frequency of the ring oscillator clock signal. Based on the ringoscillator clock frequency, the system clock divider parameter and theSAR clock divider parameter may be calculated and transmitted toprocessing circuitry 640 to generate the desired system clock and SARclock. Next, processing circuitry 640 may be used to individuallymeasure the resultant system clock frequency and the resultant SAR clockfrequency to verify they are running at the correct frequencies.Dithering may be enabled or disabled during these measurements, butshould be enabled if reducing possible EMI is desired.

FIGS. 10A-10B are flow diagrams illustrating one example of a method 700that may be carried out by a logic circuitry package, such as logiccircuitry package 400 a-400 d, or by processing circuitry 424, 600, or640. As illustrated in FIG. 10A at 702, at least one logic circuit ofthe logic circuitry package may receive, via the interface, a request toturn on a clock generator of the logic circuitry package. At 704, the atleast one logic circuit may receive, via the interface, a requestselecting an internal clock signal to sample. At 706, the at least onelogic circuit may receive, via the interface, a reference clock signal.At 708, the at least one logic circuit may transmit, via the interface,a digital value indicating a count of cycles of the selected internalclock signal during a predetermined number of cycles of the referenceclock signal. The digital value may include two bytes. In one example,the predetermined number of cycles of the reference clock signal equalseight cycles.

In some examples, the clock generator includes a ring oscillator (e.g.,ring oscillator 646 of FIG. 9). In this case, the request selecting aninternal clock signal to sample may indicate a ring oscillator clocksignal, a system clock signal derived from the ring oscillator clocksignal, or a successive approximation register (SAR) clock signalderived from the ring oscillator clock signal.

As illustrated in FIG. 10B, at 710 the at least one logic circuit mayfurther receive, via the interface, a system clock divider parameter toconfigure a system clock divider (e.g., system clock divider 652) todivide the ring oscillator clock signal to generate the system clocksignal. At 712, the at least one logic circuit may receive, via theinterface, a SAR clock divider parameter to configure a SAR clockdivider (e.g., SAR clock divider 654) to divide the ring oscillatorclock signal to generate the SAR clock signal. The interface may includean I2C interface (e.g., I2C interface 642), and the reference clocksignal may include an I2C clock signal received through the 120interface.

FIGS. 11A-11B are flow diagrams illustrating another example of a method720 that may be carried out by a logic circuitry package, such as logiccircuitry package 400 a-400 d, or by processing circuitry 424, 600, or640. As illustrated in FIG. 11A, at 722 method 720 includes turning on,via a print apparatus logic circuit, a ring oscillator (e.g., ringoscillator 646 of FIG. 9) of a logic circuitry package. At 724, method720 includes selecting, via the print apparatus logic circuit, aninternal clock signal of the logic circuitry package to sample. At 726,method 720 includes initiating, via the print apparatus logic circuit, asampling of the selected internal clock signal of the logic circuitrypackage. At 728, method 720 includes counting, via the logic circuitrypackage, cycles of the selected internal clock signal during apredetermined number of cycles of a reference clock signal. At 730,method 720 includes calculating, via the print apparatus logic circuit,the frequency of the selected internal clock signal based on the cyclecount.

Calculating the frequency of the selected internal clock signal includesdividing the cycle count by the predetermined number of cycles times theclock period of the reference clock signal. In one example, initiatingthe sampling of the selected internal clock signal includes transmittinga command from the print apparatus logic circuit to the logic circuitrypackage through an I2C interface. In this case, the reference clock mayinclude an I2C clock of the command. In one example, selecting theinternal clock signal includes selecting one of a ring oscillator clocksignal, a system clock signal derived from the ring oscillator clocksignal, or a successive approximation register (SAR) clock signalderived from the ring oscillator clock signal.

As illustrated in FIG. 11B, at 732 method 720 may further includesetting a system clock divider parameter to generate the system clocksignal by dividing the ring oscillator clock signal based on the systemclock divider parameter. At 734, method 720 may further include settinga SAR clock divider parameter to generate the SAR clock signal bydividing the ring oscillator clock signal based on the SAR clock dividerparameter.

FIGS. 12A-12D are flow diagrams illustrating another example of a method740 that may be carried out by a logic circuitry package, such as logiccircuitry package 400 a-400 d, or by processing circuitry 424, 600, or640. As illustrated in FIG. 12A, at 742 at least one logic circuit of alogic circuitry package may receive, via the interface, a request and areference clock signal. At 744, the at least one logic circuit maytransmit, via the interface, a digital value indicating a count inresponse to the request and the reference clock signal, wherein thedigital value varies based on the reference clock signal. In oneexample, the at least one logic circuit includes a clock generator toderive the count based on the received reference clock signal.

In some examples, the request includes a first read request and a secondread request, the first read request and the second read requestsincluding a different read address. In this case, as illustrated in FIG.12B, at 746 the at least one logic circuit may further receive, via theinterface, the first read request. At 748, the at least one logiccircuit may transmit, via the interface, a first portion of the digitalvalue in response to the first read request. At 750, the at least onelogic circuit may receive, via the interface, the second read request.At 752, the at least one logic circuit may transmit, via the interface,a second portion of the digital value in response to the second readrequest. In one example, the first portion of the digital value includesmost significant bits of the digital value and the second portion of thedigital value includes least significant bits of the digital value.

As illustrated in FIG. 12C, at 754 the at least one logic circuit mayfurther receive, via the interface, a first request. At 756, the atleast one logic circuit may receive, via the interface, a firstreference clock signal. At 758, the at least one logic circuit maytransmit, via the interface, a first digital value indicating a firstcount during a predetermined number of cycles of the first referenceclock signal in response to the first request. At 760, the at least onelogic circuit may receive, via the interface, a second request. At 762,the at least one logic circuit may receive, via the interface, a secondreference clock signal. At 764, the at least one logic circuit maytransmit, via the interface, a second digital value indicating a secondcount during the predetermined number of cycles of the second referenceclock signal in response to the second request, wherein the firstdigital value is different from the second digital value.

In one example, the first request is to select an internal clock signalto sample. In this case, the first digital value indicates a first countof cycles of the selected internal clock signal during the predeterminednumber of cycles of the first reference clock signal. Also in this case,the second request is to select the internal clock signal to sample andthe second digital value indicates a second count of cycles of theselected internal clock signal during the predetermined number of cyclesof the second reference clock signal. In some examples, the firstreference clock signal has a first frequency and the second referenceclock signal has a second frequency different from the first frequency.In one example, the first frequency is greater than the secondfrequency, and the first digital value is less than the second digitalvalue. In another example, the first frequency is less than the secondfrequency, and the first digital value is greater than the seconddigital value.

The at least one logic circuit may include a clock generator to generatean internal clock signal. As illustrated in FIG. 12D, at 766 the atleast one logic circuit may further receive, via the interface, arequest to turn on the clock generator prior to receiving the firstrequest. In one example, the clock generator includes a ring oscillator.In this case, the first request selecting the internal clock signal tosample may indicate a ring oscillator clock signal. In some examples,the first digital value and the second digital value each include twobytes. The predetermined number of cycles of the first reference clocksignal and the second reference clock signal may equal eight cycles. Theinterface may include an I2C interface, and the first reference clocksignal and the second reference clock signal may each include an I2Cclock signal received through the I2C interface.

FIGS. 13A-13D are flow diagrams illustrating another example of a method800 that may be carried out by a logic circuitry package, such as logiccircuitry package 400 a-400 d, or by processing circuitry 424, 600, or640. As illustrated in FIG. 13A, at 802 at least one logic circuit of alogic circuitry package may receive, via the interface, a request, adither parameter, and a reference clock signal. At 804, the at least onelogic circuit may transmit, via the interface, a digital valueindicating a count in response to the request, the dither parameter, andthe reference clock signal, wherein the digital value varies based onthe dither parameter. In one example, the at least one logic circuitincludes a clock generator to derive the count based on the receiveddither parameter and the reference clock signal.

In some examples, the request may include a first read request and asecond read request, the first and second read requests including adifferent read address. In this case, as illustrated in FIG. 13B, at 806the at least one logic circuit may further receive, via the interface,the first read request. At 808, the at least one logic circuit maytransmit, via the interface, a first portion of the digital value inresponse to the first read request. At 810, the at least one logiccircuit may receive, via the interface, the second read request. At 812,the at least one logic circuit may transmit, via the interface, a secondportion of the digital value in response to the second read request. Inone example, the first portion of the digital value includes mostsignificant bits of the digital value and the second portion of thedigital value includes least significant bits of the digital value.

As illustrated in FIG. 13C, at 814 the at least one logic circuit mayfurther receive, via the interface, a first dither parameter. At 816,the at least one logic circuit may receive, via the interface, a firstrequest. At 818, the at least one logic circuit may receive, via theinterface, a reference clock signal. At 820, the at least one logiccircuit may transmit, via the interface, a first digital valueindicating a first count during a predetermined number of cycles of thereference clock signal in response to the first request. At 822, the atleast one logic circuit may receive, via the interface, a second ditherparameter. At 824, the at least one logic circuit may receive, via theinterface, a second request. At 826, the at least one logic circuit maytransmit, via the interface, a second digital value indicating a secondcount during the predetermined number of cycles of the reference clocksignal in response to the second request, wherein the first digitalvalue is different from the second digital value.

In one example, the first request is to select an internal clock signalto sample. In this case, the first digital value indicates a first countof cycles of the selected internal clock signal during the predeterminednumber of cycles of the reference clock signal. Also in this case, thesecond request is to select the internal clock signal to sample, and thesecond digital value indicates a second count of cycles of the selectedinternal clock signal during the predetermined number of cycles of thereference clock signal.

In some examples, the first dither parameter corresponds to a firstfrequency and the second dither parameter corresponds to a secondfrequency different from the first frequency. In one example, the firstfrequency is greater than the second frequency, and the first digitalvalue is greater than the second digital value. In another example, thefirst frequency is less than the second frequency, and the first digitalvalue is less than the second digital value.

In one example, the at least one logic circuit includes a clockgenerator to generate an internal clock signal. In this case asillustrated in FIG. 13D, at 828 the at least one logic circuit mayfurther receive, via the interface, a request to turn on the clockgenerator prior to receiving the first request. In one example, theclock generator includes a ring oscillator. In this case, the firstrequest selecting the internal clock signal to sample indicates a ringoscillator clock signal. The first digital value and the second digitalvalue may each comprise two bytes. The predetermined number of cycles ofthe reference clock signal may equal eight cycles. In one example, theinterface includes an I2C interface, and the reference clock signalincludes an I2C clock signal received through the I2C interface.

FIGS. 14A-14B are flow diagrams illustrating another example of a method840 that may be carried out by a logic circuitry package, such as logiccircuitry package 400 a-400 d, or by processing circuitry 424, 600, or640. As illustrated in FIG. 14A at 842, at least one logic circuit ofthe logic circuitry package may receive, via the interface, a firstdither parameter. At 844, the at least one logic circuit may receive,via the interface, a first request selecting an internal clock signal tosample. At 846, the at least one logic circuit may receive, via theinterface, a first reference clock signal. At 848, the at least onelogic circuit may transmit, via the interface, a first digital valueindicating a first count of cycles of the selected internal clock signalduring a predetermined number of cycles of the first reference clocksignal. At 850, the at least one logic circuit may receive, via theinterface, a second dither parameter. At 852, the at least one logiccircuit may receive, via the interface, a second request selecting theinternal clock signal to sample. At 854, the at least one logic circuitmay receive, via the interface, a second reference clock signal. At 856,the at least one logic circuit may transmit, via the interface, a seconddigital value indicating a second count of cycles of the selectedinternal clock signal during the predetermined number of cycles of thesecond reference clock signal, wherein the first digital value isdifferent from the second digital value.

In some examples, the first reference clock signal has a first frequencyand the second reference clock signal has a second frequency differentfrom the first frequency. In some examples, the first dither parametercorresponds to a third frequency and the second dither parametercorresponds to a fourth frequency different from the third frequency. Inone example, the first frequency is greater than the second frequency,and the third frequency is less than the fourth frequency.

In some examples, the at least one logic circuit includes a clockgenerator to generate an internal clock signal. In this case asillustrated in FIG. 14B, at 858 the at least one logic circuit mayfurther receive, via the interface, a request to turn on the clockgenerator prior to receiving the first request. In one example, theclock generator includes a ring oscillator. In this case, the firstrequest selecting the internal clock signal to sample may indicate aring oscillator clock signal. The first digital value and the seconddigital value may each include two bytes. The predetermined number ofcycles of the first reference clock signal and the second referenceclock signal may equal eight cycles. In one example, the interfaceincludes an I2C interface, and the first reference clock signal and thesecond reference clock signal each include an I2C clock signal receivedthrough the I2C interface.

FIG. 15 illustrates another example of a logic circuitry package 900.FIG. 15 illustrates how the logic circuitry package 900 may generate adigital output (e.g., output count value) based on inputs including asensor ID, parameters (e.g., system clock divider parameter, SAR clockdivider parameter, dither parameter), a reference clock (e.g., an I2Cclock), and/or requests (e.g., to sample a clock signal) sent digitallyby the print apparatus. Logic circuitry package 900 includes a logiccircuit with a processor 902 communicatively coupled to a memory 904.Memory 904 may store look up table(s) and/or list(s) 906 and/oralgorithm(s) 908. Logic circuitry package 900 may also include any ofthe features of logic circuitry packages 400 a-400 d or processingcircuitry 424, 600, and/or 640 as previously described.

For example, the logic circuitry package 900 may include at least onesensor 910, or multiple sensors of different types. The logic circuitmay be configured to consult a respective sensor 910, in combinationwith the LUT(s)/list(s) 906 and/or algorithm(s) 908, based on the sensorID and calibration parameters, to generate the digital output. The atleast one sensor 910 may include a sensor to detect an effect of apneumatic actuation of the print apparatus upon the replaceable printcomponent, and/or a sensor to detect an approximate temperature, and/orother sensors. The logic circuitry package 900 may include a pluralityof sensors of different types, for example, at least two sensors ofdifferent types, wherein the logic circuit may be configured to selectand consult one of the sensors based on the sensor ID, and output adigital value based on a signal of the selected sensor.

Different sets of all the parameters are related to the different outputcount values as already explained above. The output count values may begenerated using the LUT(s) and or list(s) 906 and/or algorithm(s) 908whereby the parameters may be used as input. In addition, a signal of atleast one sensor 910 may be consulted as input for the LUT. In thiscase, the output count values may be digitally generated, rather thanobtained from analog sensor measurements or tasks. For example, logiccircuitry package 900 may implement the methods 740 and 800 of FIGS.12A-12D and 13A-13D without sampling an internal clock signal of thelogic circuitry package. In another example, analog sensor measurementsmay be used to thereafter digitally generate the output count value, notnecessarily directly converted, but rather, using a LUT, list oralgorithm, whereby the sensor signal is used to choose a portion orfunction of the LUT, list or algorithm. The example logic circuitrypackage 900 may be used as an alternative to the complex thin filmsensor arrays addressed elsewhere in this disclosure. The example logiccircuitry package 900 may be configured to generate outputs that arevalidated by the same print apparatus logic circuit designed to becompatible with the complex sensor array packages. The alternativepackage 900 may be cheaper or simpler to manufacture, or simply be usedas an alternative to the earlier mentioned packages, for example tofacilitate printing and validation by the print apparatus.

Logic circuitry package 900 may be configured to output a digital valueindicating a count in response to a request and a reference clocksignal, wherein the digital value varies based on variations of thereference clock signal. The reference clock signal may be an I2Creference clock signal. In one example, logic circuitry package 900 mayinclude a clock generator to derive the count based on the receivedreference clock signal. In another example, as illustrated in FIG. 15,logic circuitry package 900 may include a reference clock monitor 912,which may include, for example, a second timer or clock. The referenceclock monitor 912 may be adapted to monitor the frequency of the inputreference clock (e.g., 120) signal, sufficient to detect a change in thefrequency of the reference clock signal. Logic circuitry package 900 maybe configured to determine the output count for validly responding to arequest and varying reference clock signal using reference clock monitor912. In one example, the reference clock monitor 912 may be configuredto detect a variation with respect to a standard I2C clock frequency.For example, logic circuitry package 900 may be configured to output avalid clock count based on the determined (change in) I2C referenceclock signal and request using the LUT, list and/or algorithm.Similarly, logic circuitry package 900 may be configured to set anoutput count based on the request and write to a dither memory field(e.g., dither register) using the LUT, list and/or algorithm.

In one example, the logic circuitry packages described herein mainlyinclude hardwired routings, connections, and interfaces betweendifferent components. In another example, the logic circuitry packagesmay also include at least one wireless connection, wirelesscommunication path, or wireless interface, for internal and/or externalsignaling, whereby a wirelessly connected element may be considered asincluded in the logic circuitry package and/or replaceable component.For example, certain sensors may be wireless connected to communicatewirelessly to the logic circuit/sensor circuit. For example, sensorssuch as pressure sensors and/or print material level sensors maycommunicate wirelessly with other portions of the logic circuit. Theseelements, that communicate wirelessly with the rest of the logiccircuit, may be considered part of the logic circuit or logic circuitrypackage. Also, the external interface of the logic circuitry package, tocommunicate with the print apparatus logic circuit, may include awireless interface. Also, while reference may be made to power routings,power interfaces, or charging or powering certain cells, certainexamples of this disclosure may include a power source such as a batteryor a power harvesting source that may harvest power from data or clocksignals.

Certain example circuits of this disclosure relate to outputs that varyin a certain way in response to certain commands, events and/or states.It is also explained that, unless calibrated in advance, responses tothese same events and/or states may be “clipped”, for example so thatthey cannot be characterized or are not relatable to these commands,events and/or states. For these example circuits where the output needsto be calibrated to obtain the characterizable or relatable output, itshould be understood that also before required calibration (orinstallation) occurred these circuits are in fact already “configured”to provide for the characterizable output, that is, all means arepresent to provide for the characterizable output, even wherecalibration is yet to occur. It may be a matter of choice to calibrate alogic circuit during manufacture and/or during customer installationand/or during printing, but this does not take away that the samecircuit is already “configured” to function in the calibrated state. Forexample, when sensors are mounted to a reservoir wall, certain strainsin that wall over the lifetime of the component may vary and may bedifficult to predict while at the same time these unpredictable strainsaffect the output of the logic circuit. Different other circumstancessuch as conductivity of the print material, different packaging,in-assembly-line-mounting, etc. may also influence how the logic circuitresponds to commands/events/states so that a choice may be made tocalibrate at or after a first customer installation. In any of these andother examples, it is advantageous to determine (operational)calibration parameters in-situ, after first customer installation and/orbetween print jobs, whereby, again, these should be considered asalready adapted to function in a calibrated state. Certain alternative(at least partly) “virtual” embodiments discussed in this disclosure mayoperate with LUTs or algorithms, which may similarly generate, beforecalibration or installation, clipped values, and after calibration orinstallation, characterizable values whereby such alternativeembodiment, should also be considered as already configured or adaptedto provide for the characterizable output, even beforecalibration/installation.

In one example, the logic circuitry package outputs count values inresponse to read requests. In many examples, the output of count valuesis discussed. In certain examples, each separate count value is outputin response to each read request. In another example, a logic circuit isconfigured to output a series or plurality of count values in responseto a single read request. In other examples, output may be generatedwithout a read request.

Each of the logic circuitry packages 400 a-400 d, 900 described hereinmay have any feature of any other logic circuitry packages 400 a-400 d,900 described herein or of the processing circuitry 424, 600, 640. Anylogic circuitry packages 400 a-400 d, 900 or the processing circuitry424, 600, 640 may be configured to carry out at least one method blockof the methods described herein. Any first logic circuit may have anyattribute of any second logic circuit, and vice versa.

Examples in the present disclosure can be provided as methods, systemsor machine readable instructions, such as any combination of software,hardware, firmware or the like. Such machine readable instructions maybe included on a machine readable storage medium (including but notlimited to EEPROM, PROM, flash memory, disc storage, CD-ROM, opticalstorage, etc.) having machine readable program codes therein or thereon.

The present disclosure is described with reference to flow charts andblock diagrams of the method, devices and systems according to examplesof the present disclosure. Although the flow diagrams described aboveshow a specific order of execution, the order of execution may differfrom that which is depicted. Blocks described in relation to one flowchart may be combined with those of another flow chart. It shall beunderstood that at least some blocks in the flow charts and blockdiagrams, as well as combinations thereof can be realized by machinereadable instructions.

The machine readable instructions may, for example, be executed by ageneral purpose computer, a special purpose computer, an embeddedprocessor or processors of other programmable data processing devices torealize the functions described in the description and diagrams. Inparticular, a processor or processing circuitry may execute the machinereadable instructions. Thus, functional modules of the apparatus anddevices (for example, logic circuitry and/or controllers) may beimplemented by a processor executing machine readable instructionsstored in a memory, or a processor operating in accordance withinstructions embedded in logic circuitry. The term ‘processor’ is to beinterpreted broadly to include a CPU, processing unit, ASIC, logic unit,or programmable gate array etc. The methods and functional modules mayall be performed by a single processor or divided amongst severalprocessors.

Such machine readable instructions may also be stored in a machinereadable storage (e.g., a tangible machine readable medium) that canguide the computer or other programmable data processing devices tooperate in a specific mode.

Such machine readable instructions may also be loaded onto a computer orother programmable data processing devices, so that the computer orother programmable data processing devices perform a series ofoperations to produce computer-implemented processing, thus theinstructions executed on the computer or other programmable devicesrealize functions specified by block(s) in the flow charts and/or in theblock diagrams.

Further, the teachings herein may be implemented in the form of acomputer software product, the computer software product being stored ina storage medium and comprising a plurality of instructions for making acomputer device implement the methods recited in the examples of thepresent disclosure.

The word “comprising” does not exclude the presence of elements otherthan those listed in a claim, “a” or “an” does not exclude a plurality,and a single processor or other unit may fulfill the functions ofseveral units recited in the claims.

Although specific examples have been illustrated and described herein, avariety of alternate and/or equivalent implementations may besubstituted for the specific examples shown and described withoutdeparting from the scope of the present disclosure. This application isintended to cover any adaptations or variations of the specific examplesdiscussed herein. Therefore, it is intended that this disclosure belimited only by the claims and the equivalents thereof.

1-26. (canceled)
 27. A logic circuitry package for a replaceable printapparatus component comprising an interface to communicate with a printapparatus logic circuit, and at least one logic circuit configured to:receive, via the interface, a request to turn on a clock generator ofthe logic circuitry package; receive, via the interface, a requestselecting an internal clock signal to sample; receive, via theinterface, a reference clock signal; and transmit, via the interface, adigital value indicating a count of cycles of the selected internalclock signal during a predetermined number of cycles of the referenceclock signal.
 28. The logic circuitry package of claim 27, wherein theat least one logic circuit comprises a clock generator to generate theinternal clock signal.
 29. The logic circuitry package of claim 27,wherein the clock generator comprises a ring oscillator.
 30. The logiccircuitry package of claim 29, wherein the request selecting an internalclock signal to sample indicates a ring oscillator clock signal, asystem clock signal derived from the ring oscillator clock signal, or asuccessive approximation register (SAR) clock signal derived from thering oscillator clock signal.
 31. The logic circuitry package of claim30, wherein the at least one logic circuit comprises a system clockdivider to divide the ring oscillator clock signal to generate thesystem clock signal.
 32. The logic circuitry package of claim 30,wherein the at least one logic circuit comprises a SAR clock divider todivide the ring oscillator clock signal to generate the SAR clocksignal.
 33. The logic circuitry package of claim 30, wherein the atleast one logic circuit is configured to: receive, via the interface, asystem clock divider parameter to configure the system clock divider todivide the ring oscillator clock signal to generate the system clocksignal; and receive, via the interface, a SAR clock divider parameter toconfigure the SAR clock divider to divide the ring oscillator clocksignal to generate the SAR clock signal.
 34. The logic circuitry packageof claim 27, wherein the digital value comprises two bytes.
 35. Thelogic circuitry package of claim 27, wherein the predetermined number ofcycles of the reference clock signal equals eight cycles.
 36. The logiccircuitry package of claim 27, wherein the interface comprises an I2Cinterface, and wherein the reference clock signal comprises an I2C clocksignal received through the I2C interface.
 37. A logic circuitry packagecomprising: an I2C interface; a clock generator to generate a firstclock signal; a clock generator test controller to receive an I2C clocksignal through the I2C interface; and a counter controlled by the clockgenerator test controller to count cycles of the first clock signalduring a predetermined number of cycles of the I2C clock signal.
 38. Thelogic circuitry package of claim 37, further comprising: a first clockdivider to generate a second clock signal based on the first clocksignal.
 39. The logic circuitry package of claim 38, further comprising:a second clock divider to generate a third clock signal based on thefirst clock signal.
 40. The logic circuitry package of claim 39, furthercomprising: a selection circuit to pass one of the first clock signal,the second clock signal, and the third clock signal to the counter. 41.The logic circuitry package of claim 39, further comprising: a memory tostore a first clock divider parameter to configure the first clockdivider and a second clock divider parameter to configure the secondclock divider.
 42. The logic circuitry package of claim 37, furthercomprising: a first register to store most significant bits of the cyclecount; and a second register to store least significant bits of thecycle count.
 43. The logic circuitry package of claim 37, furthercomprising: a dither counter, wherein the clock generator comprises aring oscillator comprising a plurality of feedback paths controlled bythe dither counter to generate a dithered first clock signal.
 44. Areplaceable print apparatus component comprising the logic circuitrypackage of claim
 27. 45. The replaceable print apparatus component ofclaim 44, further comprising: a housing having a height, a width lessthan the height, and a length greater than the height, the heightparallel to a vertical reference axis, and the width extending betweentwo sides; a print liquid reservoir within the housing; and a printliquid output.